Traditional caching algorithms in large storage architectures (e.g., MegaRAID) inherently require region locks to avoid data inconsistency. The same buffers are often re-used for all read/writes for given strip/stripe. Hence it is required to make sure that no two Direct Memory Access (DMA) operations act on the same buffers. This effectively creates a need for serialization to make sure that no two Input/Output (I/O) commands act on the same buffer at the same time.
Unfortunately, existing caching algorithms have high latency. Another drawback to existing caching algorithms is that they are highly coupled and very difficult to decouple for purposes of achieving hardware automation.
Unlike RAID 0 and RAID 1, RAID 5 and RAID 6 would have one or two parity arms for redundancy. Having parity exposes its own challenges since each update for the data arms also results into an update for the parity. So the same algorithm that is used for RAID 0/1 would need modification as a parity update is involved.
To perform the above step there is a need for an optimized data structure to contain the information of all the data arms and parity arms. Moreover, when the caching is automated, there is a need to represent all the arms in a compact form so as to reduce the memory foot print.